Caliber DesignEnhancer software, announced by Siemens EDA at the July 2023 Design Automation Conference (DAC), has been incorporated into Samsung Foundry's Process Design Kit (PDK). The software provides multiple usage models that perform automatic layout optimization to improve power tolerance and shorten design cycles when implementing IC designs.
IC design engineers have traditionally relied on third-party place and route tools to incorporate design-for-manufacturing (DFM) optimization. However, it often requires multiple, lengthy runs to converge on a “DRC clean” solution.
Source: Siemens EDA
Caliber DesignEnhancer supports automatic layout optimization during IC design and assembly stages, allowing IC designers to improve design manufacturability and circuit reliability while providing “DRC clean” designs for faster tapeout. will help you. Here, its via insertion usage model automatically inserts additional vias into the layout that are compatible with Caliber nmDRC to reduce resistance and reduce both voltage (IR) drops and electrostatic discharge (ESD) events in IC designs. can be kept to a minimum.
Siemens EDA claims its layout tools can significantly reduce turnaround time and reduce EM/IR issues for design teams while preparing layouts for physical verification. Caliber DesignEnhancer optimizes IC designs by quickly and accurately reducing or eliminating IR drop and electromigration (EM) issues.
This is accomplished by automatically implementing “CaliberCorrect-by-Construction” design layout changes very early in the IC design and verification process. Luigi Rolandi, senior director of research and development at STMicroelectronics, acknowledged that Caliber DesignEnhancer has proven useful in addressing and resolving out-of-spec resistance and IR drop issues.
JoongWon Jeon, distinguished engineer on Samsung Electronics' foundry technology development team, also acknowledged that Caliber DesignEnhancer has provided mutual customers with step-function improvements in via insertion efficiency. “This reduces turnaround time compared to traditional approaches to problems.” For example, traditional place-and-route processes often require design teams to run multiple times, but Samsung PDK's Caliber DesignEnhancer helps IC designers achieve significant first-pass gains.
Caliber DesignEnhancer integrates with all major design and implementation environments using industry interface standards, comes with kits for all major foundries, and supports designs from 130 nm to 2 nm process nodes .
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