The resulting waveforms presented here serve as empirical evidence supporting our assertion of high gain and efficiency. This dynamic modelling approach enhances our understanding of the converter’s operation, reinforcing our claim of superior performance across diverse scenarios. The projected converter is designed for an output power of 100 W, with an output voltage of 54 V. With input voltages of 12 V and 24 V, they can be produced at a duty ratio of 25%. The load resistance is calculated using the basic formula as 29.1 Ω. To reduce the converter size, it is advisable to take higher switching frequencies (f_{s}), however, for the proposed simulation and design 50 kHz includes Two inductors and Two capacitors. With the considerable current and voltage ripples on the inductors and capacitors, respectively. The energy component values are calculated and are observed in Table 4.

### Theoretical calculations

We explore the theoretical calculations for the proposed converter, examining three distinct cases. For each case, the theoretical framework is summarized in the Table 5.

### Simulation circuit for different cases

#### Case-1

In this case, the DC source 1 acts as the primary source, providing an input voltage of 12 V and yielding an output voltage of 36 V. Switches \({M}_{1}\) and \({M}_{4}\) are both in the ON state, with a duty ratio of 0.25 for \({M}_{1}\) and 0.75 for \({M}_{4}\). The Simulink diagram for Case-1 is depicted in Fig. 7.

While Figs. 8 and 9 depicts the corresponding output voltage and output current waveforms. From the waveforms, the rise time can be determined as 0.002 s and the settling time is 0.014 s.

#### Case-2

In this case, the DC source 1 acts as the primary source, providing an input voltage of 24 V and yielding an output voltage of 72 V. Switches \({M}_{2}\) and \({M}_{4}\) are both in the ON state, with a duty ratio of 0.25 for *M*_{2} and 0.75 for \({M}_{4}\). The Fig. 10 displays the Simulink diagram for Case 2.

While Figs. 11 and 12 depicts the corresponding output voltage and output current waveform.

#### Case-3

In this case, the DC source 1 acts as the primary source, providing an input voltage of 36 V and yielding an output voltage of 108 V. Switches \({M}_{3}\) and \({M}_{4}\) are both in the ON state, with a duty ratio of 0.25 for \({M}_{3}\) and 0.75 for \({M}_{4}\). The Fig. 13 displays the Simulink diagram for Case 3. While Figs. 14 and 15 depict the corresponding output voltage and current waveform.

This Table 6 comprehensively compares the parameters of performance for each of the three instances, including input voltage, input current, input power, output voltage, output current, output power, efficiency, and ripple factor.

We have examined each of the three cases from the preceding discussion individually. The Simulink diagram presented visually represents the proposed converter, which incorporates inductors, capacitors, diodes, four switches with phase delay, and is powered by both DC source 1 and DC source 2. The Fig. 16 displays the Simulink diagram for proposed converter.

Figure 17 represents the input DC voltage waveform and Fig. 18 represents the input current plotted using MATLAB simulation. A 12 V & 24 V DC input voltage is considered when designing the proposed topology. Similarly, it can be observed that the input current waveform is continuous.

Figure 18 shows that the input current never reaches zero, indicating continuous current conduction from the input. The observed current interval from 1 to 200.

The inductors \({L}_{a}\) & \({L}_{b}\) are charged when the active switches are in ON state and they will discharge their energy when the active switches are in OFF state. Figure 19 shows the simulated inductor (\({L}_{a}\)) current waveforms and inductor voltage waveforms, respectively under steady-state operation. Figure 20 shows the simulated inductor(b) current waveforms and inductor voltage waveforms under steady-state operation. The capacitor \({C}_{a}\) and \({C}_{b}\) discharge the energy when the active switches are turned on, and charges when the switch is turned off. The capacitor voltage waveforms can be observed in Figs. 23 and 24. The capacitor current waveforms can be observed in Figs. 25 and 26.

Under the steady state condition, the graph shows a stable output. Figure 19 shows the current from 10 to 12 during the time interval between 0.1664 and 0.1666, whereas the voltage from − 100 to 40 during the time interval between 0.1664 and 0.1666. Under the steady state condition, the graph shows a stable output. Figure 20 shows the current from − 8 to − 2 during the time interval between 0.0667 and 0.0668, whereas the voltage is from − 100 to 0 during the time interval between 0.0667 and 0.0668.

Under the steady state condition, the graph shows a stable output. Figure 21 shows the capacitor (\({C}_{a}\)) voltage from 20 to 45 during the time interval between 0.0606 and 0.0608, whereas the capacitor (\({C}_{a}\)) current from 0 to 25 during the time interval between 0.0606 and 0.0608.

Under the steady state condition, the graph shows a stable output. Figure 22 shows the capacitor (\({C}_{b}\)) voltage from 0 to 150 during the time interval between 0.0845 and 0.0846, whereas the capacitor (\({C}_{b}\)) current from 0 to 30 during the time interval between 0.0845 and 0.0846.

The Gate pulse of switches with phase delay is shown in Fig. 23. The switches are operated with a duty ratio of 25% and they are turned ON and OFF (altered for 50,000 times in a second) i.e., switching frequency is 50,000 Hz.

The voltage and current across the diodes are shown in Fig. 24. The diodes are operated with a duty ratio of 25% and they are turned ON and OFF (altered for 50,000 times in a second) i.e., switching frequency is 50,000 Hz.

In Fig. 24, the negative voltage across diode (\({d}_{a}\)) is attributed to three specific cases. This occurs when the current through the diode is zero, indicating that the diode is in a reverse bias state.

In Fig. 25, The diode is initially reverse-biased, and the current is zero. At around 0.1 s, the diode becomes forward-biased, and the current begins to flow. The current increases rapidly to a peak value of 0.05 A at around 0.15 s.

Finally, the simulated output waveforms are shown in the Figs. 26 & 27 of the proposed converter. For a 100 W power, the proposed converter is designed with an output voltage of 108 V. A load of 29.1 Ω resistance is used at the output and hence the DC output current can be given as 3.468 A theoretically. Figures 26 & 27 shows the simulated output voltage waveform and DC current voltage waveform. The simulated value is approximately 100.02 V and is much closed to the computed theoretical value.

Figures 26 & 27 show that the input and output voltage waveforms of the proposed converter are related. At a frequency of 50 Hz and a duty cycle of 0.25, the output voltage consistently reaches 100 V and 3.58A.

### Performance of proposed converter

An analysis is conducted on the suggested converter’s efficiency, ripple factor, output power, output current, output voltage, and the voltage stresses placed on the active and passive parts. The simulated values for various duty ratios for various circumstances are shown in Tables 7, 8 and 9.

From Table 7, the analysis of the Multi-Input SEPIC converter’s performance at various duty cycles sheds light on its operation. At lower duty cycles, such as 0.1, it attains peak efficiency of 95.23% and demonstrates a low ripple factor, indicating optimal performance. However, as the duty cycle increases beyond 0.4, both efficiency and ripple factor deteriorate significantly. Input and output currents remain relatively stable across different duty cycles, while the input voltage remains constant at 12 V. This analysis underscores the critical importance of carefully selecting the duty cycle to fine-tune the Multi-Input SEPIC converter’s efficiency and ripple characteristics for specific applications.

From Table 8, the analysis of the Multi-Input SEPIC converter’s performance at various duty cycles sheds light on its operation. At lower duty cycles, such as 0.1, it attains peak efficiency of 96.3% and demonstrates a low ripple factor, indicating optimal performance. However, as the duty cycle decreases beyond 0.4, both efficiency and ripple factor deteriorate significantly. Input and output currents remain relatively stable across different duty cycles, while the input voltage remains constant at 24 V. This analysis underscores the critical importance of carefully selecting the duty cycle to finetune the Multi-Input SEPIC converter’s efficiency and ripple characteristics for specific applications.

From Table 9, the analysis of the Multi-Input SEPIC converter’s performance at various duty cycles sheds light on its operation. At lower duty cycles, such as 0.1, it attains peak efficiency of 96.66% and demonstrates a low ripple factor, indicating optimal performance. However, as the duty cycle increases beyond 0.4, both efficiency and ripple factor deteriorate significantly. Input and output currents remain relatively stable across different duty cycles, while the input voltage remains constant at 36 V. This analysis underscores the critical importance of carefully selecting the duty cycle to fine-tune the Multi-Input SEPIC converter’s efficiency and ripple characteristics for specific applications.

It can be observed that the highest efficiency point is achieved at duty ratio 0.1 < d > 0.75. The proposed converter is designed with duty ratio of 25% but the highest efficiency point might occur at this duty ratio. It is also observed that the efficiency is quite higher (96%) even at lower duty ratios i.e., from 10 to 75%. And the ripple factor is under the universal limit point that is below 10% percent up to the duty ratio of 75%.

Figure 28 shows the Input power for three cases with different duty cycles. It is observed that the Input power remains constant for various duty cycles, ranging from 0.1 to 0.75, in all three cases.

The output voltage for three scenarios with various duty cycles is displayed in Fig. 29. In all three scenarios, it is seen that the output voltage stays constant across a range of duty cycles, from 0.1 to 0.75.

Figure 30 shows the Output power for three cases with different duty cycles. It is observed that the Output power remains constant for various duty cycles, ranging from 0.1 to 0.75, in all three cases.

Figure 31 shows the efficiency for three cases with different duty cycles. It is observed that the efficiency remains constant for various duty cycles, ranging from 0.1 to 0.75, in all three cases.

Figure 32 shows the Ripple factor for three cases with different duty cycles. It is observed that the Ripple factor remains constant for various duty cycles, ranging from 0.1 to 0.75, in all three cases.

### Comparisons with existing topologies

The Table 10 initially shows that the proposed converter can be compared with various traditional converters, offering significant advantages and finding numerous applications^{31}. This proposed converter features an equal number of sources, high efficiency, and fewer diodes and relays. It also exhibits lower voltage stress than other converters^{34}. In terms of the number of power switches (bidirectional), it stands out by requiring only two switches, while other converters typically have more^{36}. The Multi-Input SEPIC converter boasts fewer diodes compared to traditional converters, which often require 5 or 3 diodes^{33}. Furthermore, the Multi-Input SEPIC converter achieves an efficiency of over 96%, surpassing the lower efficiency percentages of 95%, 94%, and 88%-94% seen in other converters^{35}. When comparing these aspects with the Multi-Input SEPIC converter, it becomes evident that it excels in numerous aspects and applications^{34}.

Figures 33, 34, and 35 present a comprehensive comparison of various converters with the proposed Multi-Input SEPIC converter across different aspects. The data clearly demonstrates that the Multi-Input SEPIC converter out performs all traditional converters.